Digital Systems & Microprocessor Design (H7068)
Note to prospective students: this content is drawn from our database of current courses and modules. The detail does vary from year to year as our courses are constantly under review and continuously improving, but this information should give you a real flavour of what it is like to study at Sussex.
We’re currently reviewing teaching and assessment of our modules in light of the COVID-19 situation. We’ll publish the latest information as soon as possible.
Digital Systems and Microprocessor Design
Module H7068
Module details for 2024/25.
15 credits
FHEQ Level 5
Module Outline
This module introduces you to the world of digital logic and to the design of microprocessors. Thanks to the current explosion of connected devices, the Internet of Things, autonomous vehicles, wearable and mobile devices, and of Artificial Intelligence, there is a growing industrial push to include advanced functionalities in hardware to achieve ultra-high performance or ultra-low power. Understanding the design of digital logic or custom processors will enable you to apply for exciting jobs in these domains and others.
In this module you will learn how to design digital logic, starting from simple combinational circuits and then designing and analysing ever more complex sequential circuits, culminating in the ÄûÃÊÊÓƵ Processor – a processor which you will learn to program and then extend its architecture to give it improved hardware functionalities.
This module gives you a solid foundation of computer engineering and will allow you to progress to study embedded systems and advanced hardware architectures in the following years.
Module Topics
This module introduces students to the following topics:
· digital basics and combinational logic design
· Boolean algebra
· design of combinational circuits
· standard combinational components
· implementation technologies
· introduction to VHDL
· basic language elements
· combinational & sequential coding
· levels of abstraction
· simulation
· design flow to target device
· sequential logic
· bistable
· latches & flip-flops
· Finite State Machines (FSM) models, State diagrams
· analysis and synthesis of sequential circuits
· standard sequential components
· Register Transfer-Level design
· datapaths
· control units
· microprocessor systems
· computer arithmetic
· central processing unit, ALU, memory, I/O
· architecture, busses
· instruction set
· assembly language programming
The syllabus thus addresses the AHEP4 Learning Outcomes: C1, M1, C2, M2, C3, M3, C4, M4, C6, M6, C9, M9, C12, M12, C13, M13, C17, M17
Library
Core reading:
1) Digital Logic and Microprocessor Design with VHDL, E. O. Hwang, Thomson, 2006.
Background reading:
1) Digital Systems Design using VHDL, C. H. Roth & L. K. John, Thomson, 2008.
2) Logic and Computer Design Fundamentals, 4th ed., M. M. Mano & C. R. Kime, Pearson, 2008.
3) Fundamentals of Logic Dsign, 6th ed., C. H. Roth & L. L. Kinney, Cengage, 2010.
Module learning outcomes
Have knowledge of combinational and sequential design concepts and their design application methods.
Demonstrate the ability to apply combinational and sequential concepts through the use of design and VHDL coding, outside of the context in which they were first studied.
Have critical understanding of the digital processes in low-complexity microprocessor systems.
Demonstrate practical skills in the use of a modern suite of EDK software and target hardware.
| Type | Timing | Weighting |
|---|---|---|
| Computer Based Exam | Semester 1 Assessment | 60.00% |
| Coursework | 40.00% | |
| Coursework components. Weighted as shown below. | ||
| Test | T1 Week 2 | 5.00% |
| Project | T1 Week 11 | 75.00% |
| Test | T1 Week 4 | 5.00% |
| Test | T1 Week 8 | 5.00% |
| Test | T1 Week 10 | 5.00% |
| Test | T1 Week 6 | 5.00% |
Timing
Submission deadlines may vary for different types of assignment/groups of students.
Weighting
Coursework components (if listed) total 100% of the overall coursework weighting value.
| Term | Method | Duration | Week pattern |
|---|---|---|---|
| Autumn Semester | Laboratory | 2 hours | 11111111111 |
| Autumn Semester | Lecture | 1 hour | 11111111111 |
| Autumn Semester | Lecture | 2 hours | 11111111111 |
How to read the week pattern
The numbers indicate the weeks of the term and how many events take place each week.
Dr Leonardo Garcia Garcia
Assess convenor
/profiles/456232
Please note that the University will use all reasonable endeavours to deliver courses and modules in accordance with the descriptions set out here. However, the University keeps its courses and modules under review with the aim of enhancing quality. Some changes may therefore be made to the form or content of courses or modules shown as part of the normal process of curriculum management.
The University reserves the right to make changes to the contents or methods of delivery of, or to discontinue, merge or combine modules, if such action is reasonably considered necessary by the University. If there are not sufficient student numbers to make a module viable, the University reserves the right to cancel such a module. If the University withdraws or discontinues a module, it will use its reasonable endeavours to provide a suitable alternative module.